In last four decades, the semiconductor industry has been developed continuously to fabricate integrated circuits with highly effective and densely packed devices. In the application of integrated circuits, memory chips is one of the most important chips in the application of electronic products. With the fast growth of computer, communication, and consumer electronic devices, the need for high density and low cost memory chips, either volatile memories like DRAMs (dynamic random access memories) and SRAMs (static random access memories) and non-volatile memories like flash memories, is increasing quickly for improving the functional characteristics of the devices.
Typically, a single chip may include more than a million or even a billion devices to expand memory capacity or functional characteristics of integrated circuits. Taking DRAMs as an example, the capacity of a single chip has been raised from 16 megabytes, 64 megabytes to 256 megabytes or even higher capacities.
In general, the construction of a DRAM cell mainly includes an operating transistor and a storage cell composed mainly of a capacitor. For increasing the device density of memory cells in an unit area, the size of the operating transistor and the capacitor must be reduced without damaging the operational characteristics and the storage capacity of the capacitor. Several different methods, such as the re-construction of the shape of the storage electrode and the selection of the materials of the electrode and dielectrics, had been proposed to increase the storage capacity of a small size cell.
In the present stage technology of semiconductor fabrication, dielectrics with high dielectric constant, or namely high k dielectrics, are employed in the fabrication of both volatile and non-volatile memory cells to improve their functional characteristics. High k dielectrics such as barium strontium titanate (BST) and lead zirconate titanate (PZT) are well known to be good candidates for DRAM higher than 4 gigabyte and high density, highly capacitive non-volatile memories.
In addition to the selection of dielectrics, another approach to increase the performance of DRAM cell is by increasing surface area of electrodes to increase storage capacity. One of conventional approaches on increasing the surface area of electrodes is to re-construct the shape of the bottom electrode, in order to increase the surface area with the re-constructed shape like laterally extended fins or upwardly extended crowns. In the development of capacitors for high-density dynamic random access memory cells, various kinds of crown-shaped structures of the capacitor electrode have been proposed to increase the surface area of a single electrode.
However, in the conventional semiconductor fabrication process, the conventional crown shape or fin-like shape are constructed with the combination of conductive parts to form the final structure. Generally, more than one deposition process of conductive layers like doped polysilicon are carried out to respectively form the extended parts of the electrode. The extension of fabrication process with multiple polysilicon depositions generally decrease the throughput and the efficiency of fabricating semiconductor devices. In addition, a conductive electrode formed with the combination of multiple depositions of conductive layers generally has the problems of degradation in conductivity, strength, and reliability under the structure having several contact interfaces between deposited layers.